1. Field of the Invention
The present invention relates to ESD protection circuits and, more particularly, to an ESD protection circuit that can tolerate a negative input voltage during normal (non-ESD) operation.
2. Description of the Related Art
During normal operation, the inputs and outputs of most CMOS chips usually range between ground and the supply voltage. However, for certain current switched output drivers that are transformer coupled, the voltage levels at the output pads can swing below ground during normal circuit operation.
FIG. 1 shows a circuit diagram that illustrates a prior art output driver 100 that is current switched and transformer coupled. As shown in FIG. 1, output driver 100 includes two PMOS transistors, P1 and P2, that steer current from the VDD power supply to ground through the primary windings of transformer T1. PMOS transistors P1 and P2 are driven by a current source 112, that generates a current ISRC. In normal circuit operation, PMOS transistor P1 will be on and PMOS transistor P2 will be off, or vice versa.
When PMOS transistor P1 is on and PMOS transistor P2 is off, the ISRC current will flow from the VDD power supply to ground through PMOS transistor P1, PMOS transistor P3, and the transformer primary winding connected to PAD Y1. Similarly, when PMOS transistor P2 is on and PMOS transistor P1 is off, the ISRC current will flow from the VDD power supply to ground through PMOS transistor P2, PMOS transistor P4, and the transformer primary winding connected to PAD Y2.
The two current paths described above cause the primary current in transformer T1 to reverse direction. This current reversal, in turn, causes the secondary voltage in transformer T1 to reverse its polarity, generating a logic 1 or a logic zero.
As further shown in FIG. 1, output driver 100 includes a PMOS transistor P3 that is connected to transistor P1, and a pad Y1 that is connected to transistor P3. Output driver 100 also includes a PMOS transistor P4 that is connected to transistor P2, and a pad Y2 that is connected to transistor P4.
Transistors P3 and P4, which have their gates connected to an intermediate reference voltage (VREF), are cascode devices. Thus transistors P3 and P4 reduce the maximum voltage across transistors P1 and P2 by approximately a factor of two. For example, when the power supply voltage is 3.3V and the maximum negative swing is −1.4V, then transistors P3 and P4 reduce the maximum voltage drop across transistors P1 and P2 from 4.7V (3.3V+1.4V) to approximately 2.35V.
As shown in FIG. 1, output driver 100 includes a transformer T1 that has a primary winding PW, a secondary winding SW, and a core CR. In addition, transformer T1 also includes a center tap that is connected to ground, and a pair of identical resistors R1 and R2 that are connected between the center tap and pads Y2 and Y1, respectively. The resistors R1 and R2, in turn, are used to control the impedance seen at the transformer secondary winding SW.
During normal circuit operation, transistors P1 and P2 steer the ISRC current to ground through transformer T1 and resistors R1 and R2. Thus, as shown in FIG. 1, the steered ISRC current causes the voltages at output pads Y1 and Y2 to range from +1.4V to −1.4V. Although the +1.4V level is quite acceptable, the −1.4V level creates a serious problem for the ESD protection circuitry that is connected to pads Y1 and Y2.
FIG. 2 shows a circuit diagram that illustrates an example of a prior art ESD protection circuit 200 connected to output driver 100. As discussed in greater detail below, ESD protection circuit 200 has a serious limitation that prevents the voltages on pads Y1 and Y2 of output driver 100 from reaching the required minimum voltage level of −1.4V.
Referring to FIG. 2, ESD protection circuit 200 includes two diodes, D1 and D2, that are connected to pad Y1. The cathode of diode D1 is connected to the power supply voltage VDD, and the anode of diode D1 is connected to pad Y1. Furthermore, the cathode of diode D2 is connected to pad Y1, and the anode of diode D2 is connected to the ground line.
Similarly, ESD protection circuit 200 also includes two diodes, D3 and D4, that are connected to pad Y2. The cathode of diode D3 is connected to the power supply voltage VDD, and the anode of diode D3 is connected to pad Y2. Furthermore, the cathode of diode D4 is connected to pad Y2, and the anode of diode D4 is connected to the ground line.
Referring to FIG. 2, ESD protection circuit 200 also includes an ESD switch 210 which, in the FIG. 2 example, is implemented with an NMOS transistor N1. During normal (non-ESD) operating conditions, switch 210 (e.g. transistor N1) will remain off. However, during an ESD event, switch 210 (e.g. transistor N1) will turn on in order to conduct ESD current between the two pads that are being zapped.
For example, if pad Y2 is zapped positive with respect to pad Y1, ESD current will flow from pad Y2 to pad Y1 through the following series of circuit elements: diode D3, switch 210, and diode D2. Similarly, if pad Y1 is zapped positive with respect to pad Y2, ESD current will flow from pad Y1 to pad Y2 through the following series circuit elements: diode D1, switch 210 and diode D4.
Referring to FIG. 2, it can be seen that when pad Y2 attempts to reach −1.4V during normal (non-ESD) circuit operation, diode D4 will conduct current in the forward direction when the output voltage at pad Y2 reaches approximately −0.7V. This limits the minimum output voltage at pad Y2 to approximately −0.7V, only one forward diode drop below ground. This is a serious limitation because it prevents the negative voltage level at pad Y2 from reaching the required value of −1.4V.
Similarly, when pad Y1 attempts to reach −1.4V during normal (non-ESD) circuit operation, diode D2 will conduct current in the forward direction when the output voltage at pad Y1 reaches approximately −0.7V. This limits the minimum output voltage at pad Y1 to approximately −0.7V, only one forward diode drop below ground. This is also a serious limitation because it prevents the negative voltage level at pad Y1 from reaching the required value of −1.4V.
A possible solution to the above negative voltage limitations would be to replace diode D2 in FIG. 2 with two or more diodes connected in series. Similarly, diode D4 could also be replaced with two or more diodes connected in series. For example, three diodes connected in series would allow a minimum output voltage of three forward diode drops below ground, or approximately −2.1V (−0.7V*3). Unfortunately, as described in greater detail below, this diode replacement is not possible using prior art ESD diodes.
FIGS. 3A and 3B show a cross-sectional diagram and a schematic diagram, respectively, that illustrate a prior art ESD diode D1. Diode D1 has an N+ doped region connected to a pad that forms a cathode, and a grounded P− substrate connected to the N+ doped region that form an anode. Although the N+ cathode of diode D1 is floating and can be connected to a pad, the P− anode of diode D1 cannot float because it is formed by the grounded P− substrate. Thus, for ESD purposes, two or more D1 diodes cannot be stacked (i.e. connected in series) because they do not have floating anodes.
FIGS. 4A and 4B show a cross-sectional diagram and a schematic diagram, respectively, that illustrate a prior art ESD diode D2. Diode D2 has an N− well connected to a pad (via an N+ contact region) that forms a cathode. Furthermore, diode D2 also has a P+ doped region located inside of the N− well that forms an anode.
As shown in FIGS. 4A and 4B, the P+ anode of diode D2 is floating. In addition, the N− cathode of diode D2 is also floating and is connected to a pad. Nevertheless, as shown in FIG. 4B, the N− cathode of D2 cannot go below ground by more than one forward diode drop, due to the presence of parasitic diode D3.
Referring to FIGS. 4A and 4B, parasitic diode D3 is an N−/P− diode whose cathode is formed by the N− well and whose anode is formed by the grounded P− substrate. Furthermore, the cathode of diode D3 is connected to the cathode of diode D2, and both cathodes are connected to the pad. Nevertheless, if the connected cathodes of diodes D2 and D3 receive a negative voltage with respect to ground, their negative cathode voltage will be limited to only one forward diode drop below ground. This limitation exists because parasitic diode D3 will begin to conduct current in the forward direction when its cathode voltage attempts to go more negative than one forward diode drop below ground.
Thus, even though diode D2 is a floating diode, its cathode voltage cannot go more negative than one forward diode drop below ground. Thus, for ESD purposes, two or more D2 diodes cannot be stacked (i.e. connected in series), in order to increase the allowable negative voltage drop at the pad.
In light of the above limitations, there is a definite need for an improved ESD protection circuit that will allow substantially negative voltage levels at the chip I/O pads during normal (non-ESD) circuit operation.